This invention relates to a self-diagnostic system for semiconductor memory to be used with a random logic IC tester loaded with an IC test pattern memory or with an IC tester loaded with a multibit, large-capacity memory.
The construction of a conventional semiconductor memory diagnostic system is illustrated in FIG. 6. Referring to FIG. 6, the numeral 1 designates a CPU; 2, a data generator; 3, an address generator; 4, a comparator; and 5, a memory as a subject of diagnosis.
In FIG. 6, a diagnostic sequence program is written in the CPU 1 and, in a memory write mode, an address desired to be written into the memory 5 is given by the CPU 1 to the address generator 3. The address generator 3 receives the given address and adds it to the address input of the memory 5. The data generator 2 is supplied with data from the CPU 1 to be given to the memory 5. It receives the data and transfers it to the data input of the memory 5.
When a write signal is sent from the CPU 1 to the memory 5, the latter writes the data into the address it holds.
Next, in a memory read mode, the address to be read out from the memory is given by the CPU 1 to the address generator 3. The address generator 3 receives the address and transfers it as an address input to the memory 5. The memory reads the data at the address so added and sends the data to the comparator 4. The data generator 2 is supplied with expected data by the CPU 1. It receives the expected data and sends it to the comparator 4. The comparator 4 compares the output data from the memory 5 with the expected data, determines whether they are equal or in coincidence or not, and judges that the memory 5 is functioning properly or not.
In FIG. 6, a software is used to perform these actions with all the addresses in the memory 5.
Since the software controls the verification of operation of the memory 5, a long run time required is a problem.